Registers ARM

Processor Modes

The ARM has six operating modes:

• User (unprivileged mode under which most tasks run)
• FIQ (entered when a high priority (fast) interrupt is raised)
• IRQ (entered when a low priority (normal) interrupt is raised)
• Supervisor (entered on reset and when a Software Interrupt instruction is executed)
• Abort (used to handle memory access violations)
• Undef(used to handle undefined instructions)

ARM Architecture Version 4 adds a seventh mode:

System (privileged mode using the same registers as user mode)

The Registers

• ARM has 37 registers in total, all of which are 32-bits long.

  1 dedicated program counter

  1 dedicated current program status register

  5 dedicated saved program status registers

  30 general purpose registers

• However these are arranged into several banks, with the accessible bank being governed by the processor mode. Each mode can access

a particular set of r0-r12 registers

a particular r13 (the stack pointer) and r14 (link register)

r15 (the program counter)

cpsr (the current program status register)

and privileged modes can also access

    a particular spsr (saved program status register)

Register Organisation

Accessing Registers using ARM Instructions

• No breakdown of currently accessible registers.
• All instructions can access r0-r14 directly.
• Most instructions also allow use of the PC.
• Specific instructions to allow access to CPSR and SPSR.
• Note : When in a privileged mode, it is also possible to load / store the (banked out) user mode registers to or from memory.

The Program Status Registers (CPSR and SPSRs):

Condition Code Flags:

N = Negative result from ALU flag.

Z = Zero result from ALU flag.

C = ALU operation Carried out

V = ALU operation oVerflowed

Interrupt Disable bits.

I = 1, disables the IRQ.

F = 1, disables the FIQ.

Mode Bits

M[4:0] define the processor mode.

T Bit      (Architecture v4T only)

T = 0, Processor in ARM state

T = 1, Processor in Thumb state